This invention relates to the implementation of high-rate interpolation or decimation filters on integrated circuit devices, especially programmable integrated circuit devices such as programmable logic devices (PLDs).
Finite impulse response (FIR) filters are commonly used in digital signal processing. FIR filters include interpolation and decimation filters, in which, in order to add or remove samples, respectively, by a certain factor N, each input sample has to be held while calculations for the N−1 interpolated samples are made, or each output sample has to be held while calculations for the N−1 decimated samples are made. If the filter is to operate in real time, the portion of the filter that performs those calculations has to run at N times the input sample rate (in the interpolation case) or the output sample rate (in the decimation case).
However, the filter cannot run faster than the clock rate of the device on which the filter is built. This becomes more of an issue as data rates of signals to be processed increase. If the filter is built in fixed logic, it may be possible to design the device speed to take the data rate into account. But on a programmable device, such as a PLD, one cannot know, when designing the programmable device itself, what kind of logic a user may want to program onto the device, so the device clock rate cannot be designed with a particular data rate in mind. And even with a fixed device, the ability to design to any clock rate may be limited.
In addition, the number of filter taps is directly proportional to the ratio of sample rate to transition bandwidth. Each filter tap requires at least one multiplier. Again, on a fixed device, one may be able to provide whatever number of multipliers one needs (although again, there may be reasons why there are limits to the number of multipliers), but on a programmable device, a certain number of multipliers will be provided but it is not possible to predict how many a user may need. One solution that a user may resort to is to break the filter down into stages, thereby limiting the number of multipliers required. However, the data rate increases with each stage, so the problem of the input rate for later stages (in the interpolation case), or the output rate for earlier stages (in the decimation case), exceeding the device rate may arise for this reason as well.